Solid-state image sensors are used in, for example, video cameras, and are presently realized in a number of forms including charge coupled devices (CCDs) and CMOS image sensors. These image sensors are based on a two dimensional array of pixels. Each pixel includes a sensing element that is capable of converting a portion of an optical image into an electronic signal. These electronic signals are then used to regenerate the optical image on, for example, a liquid crystal display (LCD).
Although CMOS image sensors first appeared in 1967, CCDs dominated the image sensing market after their invention in 1970. Both solid-state imaging sensors depend on the conversion of light photons into electron hole pairs in the silicon substrate when they are exposed to light. The number of electrons holes pair which are released is proportional to the number of photons or light intensity and has dependency on the light wave-length. Even though both technologies use the same physical properties, all-analog CCDs dominated vision applications because of their superior dynamic range, low fixed-pattern noise (FPN), and high sensitivity to light.
More recently, however, CMOS image sensors have gained in popularity. Pure CMOS image sensors have benefited from advances in CMOS technology for microprocessors and ASICs and provide several advantages over CCD imagers. Shrinking lithography, coupled with advanced signal-processing algorithms, sets the stage for sensor array, array control, and image processing on one chip produced using these well-established CMOS techniques. Shrinking lithography should also decrease image-array cost due to smaller pixels. However, pixels cannot shrink too much, or they have an insufficient light-sensitive area. Nonetheless, shrinking lithography provides reduced metal-line widths that connect transistors and buses in the array.
CMOS pixel arrays are at the heart of the newly developed CMOS image sensors. CMOS pixel-array construction uses active or passive pixels. Active-pixel sensors (APSs) include amplification circuitry in each pixel. Passive pixels use photodiodes to collect the photocharge, whereas active pixels can include either photodiode or photogate light sensitive regions. The first image-sensor devices used in the 1960s were passive pixel arrays, but read noise for passive pixels has been found to be high, and it is difficult to increase the passive pixel array's size without exacerbating the noise. CMOS active-pixel sensors (APSs) overcome passive-pixel deficiencies by including active circuits (transistors) in each pixel.
FIG. 14 shows a CMOS APS image sensor circuit 50 that includes a pixel array 60 and control circuitry 70.
Pixel array 60 includes a closely spaced matrix of APS cells (pixels) 90 that are arranged in rows and columns. Pixel array 60 is depicted as a ten-by-ten array for illustrative purposes only. Pixel arrays typically consist of a much larger number of pixels. Each APS cell 90 of pixel array 60 includes a light-sensing element that is capable of converting a detected quantity of light into a corresponding electrical signal at an output terminal 95. The pixels in each row are connected to a common reset control line 73 and a common row select control line 77. The pixels in each column are connected through respective output terminals 95 to an associated common column data line 80.
Control circuitry 70 includes a row decoder 73 and sense amplifiers/registers 77. A timing controller (not shown) provides timing signals to row decoder 70 that sequentially activates each row of APS cells 90 via reset control lines 74 and row select control lines 75 to detect light intensity and to generate corresponding output voltage signals during each frame interval. The timing of the imaging system is controlled to achieve a desired frame rate, such as 30 frames per second in video applications. The detailed circuitry of the row decoder 73, sense amplifiers/registers 77 and timing controller is well known to one ordinarily skilled in the art.
During operation, APS cells 90 are utilized to detect an image. When detecting a particular frame, each row of APS cells 90 may be activated to detect light intensity over a substantial portion of the frame interval. In the time remaining after the row of APS cells 90 has detected the light intensity for the frame, each of the respective pixels simultaneously generates output voltage signals corresponding to the amount of light detected by that APS cell 90. If an image is focused on the array 60 by, for example, a conventional camera lens, then each APS cell 90 generates an output voltage signal corresponding to the light intensity for a portion of the image focused on that APS cell 90. The output voltage signals generated by the activated row are simultaneously provided to column output lines 80 via output terminals 95. Column output lines 80 transmit these output voltage signals to sense amplifiers/registers 77.
In order to reduce cost of digital cameras having more than 1 million pixels, the pixel size of CMOS image sensors is constantly decreasing. The signal-to-noise ratio (SNR) in low light of such small pixel is limited on the one hand by the smaller amount of photons impinging the pixel due to it's size, and on the other hand by (almost) constant system noise due to noise cancellation in pixel level (for modern 4T APS pixel).
When pixel dimension is decreased it is sometimes desirable to share the functionality of several transistors in the pixel in order to increase optical area. FIG. 15 depicts an exemplary approach to sharing the functionality of several pixels in which a pixel group PG includes four pixels P1 to P4 from two adjacent columns and rows that share a floating diffusion FD, a source follower transistor SF, a RESET transistor RST, and a SELECT transistor SEL. Pixels P1 to P4 respectively include photodiodes Dl to D4 and transfer gate transistors TG1 to TG4 that are collectively connected to floating diffusion FD. Floating diffusion FD is connected to source follower transistor SF and shared RESET transistor RST, also common to all the pixels is the SELECT transistor SEL. The operation of pixel group PG is described, for example, in U.S. Pat. No. 6,160,281 and U.S. Pat. No. 6,657,665, both patents being incorporated herein by reference in their entirety. As set forth in those patents, the sharing arrangement shown in FIG. 15 may be extended to share up to sixteen pixels. This sharing arrangement has many advantages over other sharing schemes, and it is widely used (see, for example, Matsushita paper: M. Mitsuyoshi et. al, IEEE Jour. Of Solid State Circuits, Vol39, p2426, 2004). The main advantage of this sharing arrangement is the ability to reduce the stray capacitance of the FD, and as a result get better process control, and with clever pixel design it can significantly reduce compare to other pixel sharing schemes.
The sharing of a floating gate between several pixels opens the possibility of sharing the charge collected from two or more pixels. This is most important when illumination conditions are poor or when pixel size is decreasing below 3.0 μm. In those conditions, the charge collected in the diode is typically low compared to the pixel or system noise. In this case, and assuming that the transfer from photodiode PD to floating diffusion FD does not add additional noise, one can open two or more transfer gates TG that are connected to the same floating diffusion FD, and thus combine (sum) the charge collected in two or more diodes. Because this charge summing (“binning”) process is executed before the pixel or system amplifier, the binning process inherently increases the resulted SNR. However, there are several problems concerning this solution: the first problem is that binning produces lower resolution from the sensor simply because every two or more photo sites are read as one. The second is the special algorithm needed in order to retain color information.
Color image sensors include color filters that are superposed over the sensor's photodetectors in a one-to-one relationship (i.e., such that each photodetector receives light filtered by a single-colored filter). The color filters are typically formed as a color filter “mosaic” in which filters having three different colors are arranged in a predetermined pattern. Most color image sensors use red, green, and blue filters that are arranged in a so-called Bayer Pattern, which is disclosed, for example, in U.S. Pat. No. 3,971,065. The Bayer pattern is schematically presented for a four row, five column array in FIG. 16. Note that each row (e.g., the top row including pixels/filters G1, B2, G3, B4 and G5) includes green filters in every other position, and only one of blue and red filters in each row (e.g., the first row includes only blue filters, and the second row (R6, G7, R8, G9, R10) includes only red filters). Note also that the green filters are aligned to form diagonal lines DLA and DLB in both left-to-right and right-to-left directions, but the red and blue filters are disposed in every other position along diagonal lines DLC and DLD.
The color information in a (one chip) CMOS image sensor is retained in a process called demosaicing. With image sensors using the Bayer Pattern, the simplest demosaicing algorithm uses four adjacent pixels in order to determine the RGB values of each pixel. For a given pixel having a green filter, the green value for that pixel is determined by the signal of the pixel itself, and blue and red values are estimated from the signals generated in adjacent blue/red pixels. For example, the RGB values for the pixel/filter G7 (which includes a green filter) are: green value (signal from pixel/filter G7), red value (signal from pixel/filter R8), and blue value (signal from pixel/filter B9). For the blue or red pixel sites, average values of the nearest green pixel/filter are used. For example, the RGB values for pixel/filter R8 are: green value (signal from pixel/filters G7 and G14 divided by two), red value (signal from pixel/filter R8), and blue value (signal from pixel/filter B12). Similarly, the RGB values for pixel/filter B12 are: green value (signal from pixel/filters G7 and G13 divided by two), red value (signal from pixel/filter R8), and blue value (signal from pixel/filter B12). Other more sophisticated algorithms for demosaicing are known to those skilled in the art.
As used herein, the term “binning” refers to the summing of image information charges generated by two or more pixels in poor illumination (e.g., low light) conditions prior to sensing the charge level. When pixel level charge binning is performed it is not desirable to add data from pixels with different colors because of the loss of chromatic information. For example, combining the charge from a green pixel and the charge from a red pixel provides substantially useless information. In addition, not all color filter information is generated equally—in a poor illumination (low light) conditions, pixels that are covered with green filters typically collect orders of magnitude more charge than pixels covered with blue filters. Therefore, the charge binning process is more important for the blue pixels than from green pixels, especially in low light conditions.
FIG. 17 is a simplified diagram depicting a pixel group PGA of a conventional color image sensor that combines the 2×2 sharing scheme (described above with reference to FIG. 16) with a color filter mosaic having the conventional Bayer pattern. Pixel group PGA is representative of all pixel groups of the color image sensor. As indicated in FIG. 17, pixel group PGA includes two green pixels (P1A and P4A), one blue pixel (P2A) and one red pixel (P3A). This facilitates convenient binning of the two green signals in each pixel group, but the red and blue signals will have to be read without binning. This is the fundamental reasons why it is not beneficial to implement pixel level charge binning in a 2×2 pixel arrangement with conventional Bayer Pattern filter arrangement.
Recently, Samsung (Young Chan Kim et al; ISSC2006, p494, 2006) and Kodak (F. Chu et al, Kodak; Proc if SPIE, Vol 6065, p606903, 2006) reported pixel level charge binning in a 4×1 sharing scheme. The advantage of the 4×1 sharing scheme is that it facilitates binning two green pixels and two red or blue pixels. The main drawback of these 4×1 binning schemes compared to the 2×2 arrangement is that in most cases the resulted FD is considerably higher than in the 2×2 arrangement due too long metal lines which are needed to connect the four separated drains of the individual TG. This reduces significantly the pixel sensitivity, which is one of the most important parameters for small (<4 um) pixels.
What is needed is a CMOS image sensor that combines the highly space-efficient 2×2 pixel sharing arrangement with charge sharing on a pixel level between two green pixels and two red or blue pixels.